SoC Power Lead, Memory Subsystem

HARDWARE_ENGINEERING
USA
April 11, 2026
FULL_TIME

Job Overview

  • Date Posted
    April 11, 2026
  • Location
    USA
  • Expiration date
    --

Job Description

2026-04-07T08:29:57.942Z

89253643391247046

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 10 years of experience with memory subsystem architectures, including for mobile SoCs.
  • Experience in power management or low power design/methodology, as well as with low power architecture and power optimization techniques.
  • Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with memory subsystem architectures, cache hierarchies, system-level power and performance modeling, SoC-wide traffic analysis and optimizations, LPDDR standards, etc.
  • Excellent leadership, organizational, and communication skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Lead the definition of power requirements for Tensor mobile System-on-Chips (SoCs) to achieve Power-Performance-Area (PPA) with a primary focus on the memory subsystem (memory controller, DDRPHY, DRAM).
  • Own and drive cross-functional teams to deliver on power Key Performance Indicators (KPIs) for the memory subsystem and other major SoC IPs.
  • Propose and drive power optimizations for the memory subsystem throughout the design process from concept to mass productization.
  • Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions.
  • Represent status of SoC power to the executive leadership team.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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