Multimedia Digital Design Engineer, Silicon

HARDWARE_ENGINEERING
New Taipei City, Taiwan
نوفمبر 12, 2025
FULL_TIME

نظرة عامة على الوظيفة

  • تاريخ الإعلان
    نوفمبر 12, 2025
  • الموقع
    New Taipei City, Taiwan
  • تاريخ إنتهاء الصلاحية
    --

المسمى الوظيفي

2025-10-22T15:29:51.035Z

73094055768007366

Google welcomes people with disabilities.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

  • Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with a scripting language like Perl or Python.
  • Experience with Application-Specific Integrated Circuit (ASIC) or FPGA design verification, synthesis, timing/power analysis and Design for Testing (DFT).
  • Knowledge of high performance and low power design techniques, assertion-based formal verification, FPGA and emulation platforms and SOC architecture.
  • Knowledge of memory compression, fabric, coherence, cache, or Dynamic Random Access Memory (DRAM).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

المسؤوليات

  • Define the block level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
  • Perform RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
  • Participate in synthesis, timing/power closure, and Field-programmable Gate Array (FPGA)/silicon bring-up.
  • Participate in test plan and coverage analysis of the block and ASIC-level verification.
  • Communicate and work with multi-disciplined and multi-site teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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