Silicon Design Verification Lead, TPU, Google Cloud
نظرة عامة على الوظيفة
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تاريخ الإعلانمارس 20, 2026
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الموقع
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تاريخ إنتهاء الصلاحية--
المسمى الوظيفي
2026-02-27T13:33:15.968Z
140230310116631238
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 10 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- 8 years of experience with verification methodology such as Universal Verification Methodology (UVM).
- 4 years of experience in people management, developing employees.
- Experience with SystemVerilog, SystemVerilog Assertions (SVA) and functional coverage.
Preferred qualifications:
- Master’s degree in Electrical Engineering or a related field.
- Experience verifying digital systems using standard IP components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Experience creating and using verification components and environments in standard verification methodology.
- Experience with ASIC standard interfaces and memory system architecture.
- Experience in verification of AI/ML Accelerators.
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google’s product portfolio possible. We’re proud to be our engineers’ engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
المسؤوليات
- Develop and execute verification plans. Architect, develop and maintain verification test benches that support both random and directed testing.
- Participate in design, architecture and code reviews. Work with micro architects, architects and design teams and influence design decisions/feature intercepts.
- Lead performance validation for both pre-silicon and post-silicon. Work with emulation/FPGA prototyping teams in verifying system level use cases. Drive convergence of verification and coverage plans towards high quality and on-time tape-out. Drive methodology initiatives to improve efficiency and design quality.
- Lead or Manage a team of design verification engineers focusing on IP, Subsystem/SoC verification at unit, cluster, subsystem and full chip levels.
- Influence architectural feature level decisions with the understanding of workload performance. Adopt methodology improvements using AI and EDA capability to drive efficiency gains and innovation.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
