Silicon DFT CAD Lead

HARDWARE_ENGINEERING
India
فبراير 13, 2026
FULL_TIME

نظرة عامة على الوظيفة

  • تاريخ الإعلان
    فبراير 13, 2026
  • الموقع
    India
  • تاريخ إنتهاء الصلاحية
    --

المسمى الوظيفي

2026-02-09T15:01:14.899Z

121701173735367366

Minimum qualifications:

  • Bachelor’s degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
  • 5 years of experience in DFT design or CAD.
  • 5 years of experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
  • Experience with DFT Electronic Design Automation (EDA) tools like Tessent.
  • Experience with scripting languages like Python and Tcl.

Preferred qualifications:

  • Master’s degree with emphasis on coursework of a quantitative nature.
  • Experience architecting/developing DFT flows and methodologies.
  • Experience in DFT for a medium to complex subsystem with multiple physical partitions.
  • Proficient in developing automated workflows using Python and Tcl.
  • Proficient with IJTAG ICL, Procedure Description Language (PDL) terminology, Instrument Connectivity Language (ICL) extraction, ICL modeling with Siemens Tessent tool.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct-to-consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

المسؤوليات

  • Work with DFT design teams to understand requirements and enable scalable workflows.
  • Work across functional domains to enable development and deployment of DFT solutions like lint, for DFT execution and signoff.
  • Collaborate with EDA vendors to develop comprehensive solutions that support Google’s advanced execution flows.
  • Develop automations for various DFT design implementation and signoff.
  • Work on DFT flows with Artificial Intelligence (AI) solutions enabled for Silicon DFT.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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