Senior FPGA Design Engineer, Quantum AI
Job Overview
-
Date PostedNovember 12, 2025
-
Location
-
Expiration date--
Job Description
2025-11-07T09:29:35.347Z
87872722553447110
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 4 years of experience in Field Programmable Gate Array (FPGA) design and development.
- 4 years of experience with RTL design using Verilog or systemVerilog.
Preferred qualifications:
- Master’s or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
- 1 year of experience in technical leadership.
About the job
In this role, you will have the opportunity to contribute to transformative projects at the forefront of quantum computing research. You will contribute to the quantum team’s mission by developing digital electronics for the control and readout of our quantum computers. You will be part of a team developing electronics for our current and next generation quantum computers and, in this context, will own development projects, working with quantum engineers, software engineers, and other hardware engineers to scope out, architect, and implement FPGA based systems.
You will have a deep understanding of the FPGA development cycle, from microarchitecture, RTL development, verification, bit file generation to hardware debugging. You will take ownership of projects and deliver reliable systems. Adept debugging skills on FPGAs and debugging failures after deployment is essential for this role. You will be passionate and self motivated to guide a lean team to achieve team’s goals and employ effective communication skills to facilitate seamless collaboration across multidisciplinary teams.
The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI’s mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.
Responsibilities
- Profile and optimize FPGA designs to improve performance, latency, and power efficiency while maintaining design documentation and communicate progress and findings effectively in meetings and reviews.
- Identify and resolve issues in RTL and post-synthesis stages using debugging tools and methodologies.
- Create testbenches and plans to verify FPGA designs, ensuring functionality and correctness through simulations and testing.
- Collaborate with quantum physicists and hardware engineers to define and implement Scalable FPGA architectures optimized for quantum computing systems.
- Develop efficient microarchitecture, RTL code using Verilog/Systemverilog to realize complex digital logic designs on FPGAs. Utilize tools like Vivado or Quartus Prime to synthesize.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.